Many large scale processor devices contain complex embedded arrays, such as cache memories and banks of general purpose registers and specialized registers. It is quite common to provide these processors with Array Built In Self Test (ABIST) circuitry to test the functionality of the embedded arrays. The ABIST circuitry is usually activated immediately after power-up and performs a pass/fail test of the storage locations in the array. Prior art processors typically provide separate, localized ABIST controllers and test circuits for each embedded array.
As the size and complexity of processor chips increase, the number and complexity of the embedded arrays increase accordingly. This results in greater use of ABIST circuits on the chips as well. Increasingly, this is becoming a design limitation, due to the size and power constraints of the microprocessor chips. Even if a centralized ABIST controller is used to control multiple ABIST test circuits, each associated with an individual embedded array, a large number of global control wires must be incorporated into the chip design, increasing both complexity and noise.
There is therefore a need for systems and methods of testing distributed, embedded arrays in microprocessors that minimize the amount and the size of the ABIST test circuitry used to test the embedded arrays. There is a still further need for systems and methods of providing centralized control to a number of ABIST test circuits that minimize the number of control lines distributed across the microprocessor chip.